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Optimal VLSI Architectural Synthesis: Area, Performance and Testability 2012

Description: Like new and unused. Pages clean and unmarked. No cover wear. Images on listing, are of this book. PAPERBACK___________ Although research in architectural synthesis has been conducted for over ten years it has had very little impact on industry. This in our view is due to the inability of current architectural synthesizers to provide area-delay competitive (or "optimal") architectures, that will support interfaces to analog, asynchronous, and other complex processes. They also fail to incorporate testability. The OASIC (optimal architectural synthesis with interface constraints) architectural synthesizer and the CATREE (computer aided trees) synthesizer demonstrate how these problems can be solved. Traditionally architectural synthesis is viewed as NP hard and there­ fore most research has involved heuristics. OASIC demonstrates by using an IP approach (using polyhedral analysis), that most input algo­ rithms can be synthesized very fast into globally optimal architectures. Since a mathematical model is used, complex interface constraints can easily be incorporated and solved. Research in test incorporation has in general been separate from syn­ thesis research. This is due to the fact that traditional test research has been at the gate or lower level of design representation. Nevertheless as technologies scale down, and complexity of design scales up, the push for reducing testing times is increased. On way to deal with this is to incorporate test strategies early in the design process. The second half of this text examines an approach for integrating architectural synthesis with test incorporation. Research showed that test must be considered during synthesis to provide good architectural solutions which minimize Xlll area delay cost functions.

Price: 40 USD

Location: White Bluff, Tennessee

End Time: 2024-11-24T15:46:11.000Z

Shipping Cost: 6.5 USD

Product Images

Optimal VLSI Architectural Synthesis: Area, Performance and Testability  2012Optimal VLSI Architectural Synthesis: Area, Performance and Testability  2012

Item Specifics

Return shipping will be paid by: Buyer

All returns accepted: Returns Accepted

Item must be returned within: 30 Days

Refund will be given as: Money Back

Country/Region of Manufacture: United States

Subject Area: Architectural Theory, Educational Technology, Laboratory Technology, GEOLOGY

Educational Level: Adult & Further Education

Features: Collector's Edition

Subject: Architecture, BUILDING, Engineering & Technology, Technology, Geography & Geosciences, Geology

Personalized: No

Level: Beginner, Intermediate

Item Length: 9.3in.

Item Height: 0.3in.

Item Width: 6.1in.

Author: Mohamed I. Elmasry, Catherine H. Gebotys

Publication Name: Optimal Vlsi Architectural Synthesis

Format: Trade Paperback

Language: English

Publisher: Springer

Publication Year: 2012

Series: The Springer International Series in Engineering and Computer Science Ser.

Type: Textbook

Item Weight: 16.7 Oz

Number of Pages: Xiv, 289 Pages

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